Example embodiments of inventive concepts relate to a semiconductor device, and in particular, to a three-dimensional semiconductor memory device including three-dimensionally arranged memory cells.
Higher integration of semiconductor devices may help satisfy consumer demands for superior performance and inexpensive prices. In the case of semiconductor devices, since their integration is an important factor in determining product prices, increased integration may reduce prices. In the case of typical two-dimensional or planar semiconductor devices, since their integration is mainly determined by the area occupied by a unit memory cell, integration is greatly influenced by the level of a fine pattern forming technology. However, the extremely expensive process equipment used to increase pattern fineness sets a practical limitation on increasing integration for two-dimensional or planar semiconductor devices.
To overcome such a limitation, there have been recently proposed three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells. However, in order to send three-dimensional semiconductor memory devices into mass-production, a process technology that provides a lower manufacturing cost per bit than two-dimensional memory devices while maintaining or exceeding their level of reliability is desired.
Meanwhile, to increase an integration density of a three-dimensional semiconductor memory device, it is necessary to increase the number of memory cell layers. However, in the case where the number of the memory cell layers is increased, a stack of the memory cell layers may collapse or fall. This falling may be limited (and/or prevented) by reducing a thickness of each memory cell layer, but in this case, a cell dissolution phenomenon may occur.